The present invention relates to a semiconductor memory device, and more particularly to a three-dimensional flash memory device.
A semiconductor memory device may be either volatile or non-volatile, depending on the type of memory element and the memory architecture employed. An example of volatile memory device is dynamic random access memory (DRAM), which loses its stored information when power is interrupted or lost. Non-volatile memory device, such as NAND or NOR memory device, can retain stored information when powered off.
A semiconductor memory device normally comprises an array of memory cells. To be cost competitive, a small memory cell size is desired in order to increase device density on wafers. One way to reduce the memory cell size is to use a compact cell structure. The cell size of current NAND devices is about 4 F2, where F is the minimum feature size associated with a particular manufacturing technology. Since the minimum cell size for an array of two-dimensional cells is 4 F2, further decrease in the cell size of NAND devices would require the stacking of memory cells in the vertical direction, thereby forming three-dimensional NAND memory structures.
Information relevant to attempts to address problems associated with three-dimensional NAND devices can be found in U.S. Pat. Nos. 8,295,089 and 8,385,122. However, each one of these references suffers from one or more of the following disadvantages: multiple masking steps are required to form multiple gate contacts; word lines shared by multiple cells in the bit line direction need much larger charge pump than a two-dimensional planar device; and complicated etching steps for forming channel studs.
For the foregoing reasons, there is a need for a memory device that has a small cell size and that can be inexpensively manufactured.